System Bus
The system bus is the communication highway that connects the CPU, memory (RAM/ROM), and I/O devices. It consists of three separate buses — the address bus, data bus, and control bus — each carrying a different type of signal. Without the system bus, internal components simply cannot communicate.
Learning Objectives
- 12.3.2.4 Explain how data is transferred between different components of a computer system through the address bus, data bus, and control bus
Conceptual Anchor
The Postal System Analogy
Think of the system bus as a postal system with three lanes. The address bus is like writing the street address on an envelope — it says WHERE to deliver. The data bus is the letter inside the envelope — the actual CONTENT being sent. The control bus is the mail carrier's instructions — is this a delivery or a pickup? Regular mail or express?
What Is a Bus?
In computing, a bus is a set of parallel wires (conductors) that carry signals between components. The system bus connects three main parts:
- CPU (processor) — processes instructions
- Memory (RAM / ROM) — stores programs and data
- I/O controllers — connect to peripherals (keyboard, monitor, disk)
The system bus is divided into three sub-buses, each with a specific role:
Address Bus
| Property | Details |
|---|---|
| Purpose | Carries the memory address that the CPU wants to read from or write to |
| Direction | Unidirectional — signals flow only from CPU → memory/I/O |
| Width | Determines maximum addressable memory (e.g., 32-bit = 2³² = 4 GB) |
| Carries | Memory addresses only (not data or instructions) |
Address Bus Width Formula
Maximum addressable memory = 2n locations, where n = number of address lines.
- 16-bit address bus → 216 = 65,536 addresses (64 KB)
- 32-bit address bus → 232 = 4,294,967,296 addresses (4 GB)
- 64-bit address bus → 264 = 16 exabytes (theoretical max)
Data Bus
| Property | Details |
|---|---|
| Purpose | Carries the actual data and instructions between components |
| Direction | Bidirectional — data flows both ways (CPU ↔ memory, CPU ↔ I/O) |
| Width | Determines how much data can be transferred at once (e.g., 64-bit = 8 bytes per transfer) |
| Carries | Data values, instructions, and results |
A wider data bus means more data per transfer → better performance. A 64-bit data bus transfers 8 bytes at once, while a 32-bit bus transfers only 4 bytes.
Control Bus
| Property | Details |
|---|---|
| Purpose | Carries control signals that coordinate and manage operations |
| Direction | Bidirectional — some signals go from CPU, some come to CPU |
| Carries | Timing signals, read/write commands, interrupts, status indicators |
Key Control Signals
| Signal | Purpose | Direction |
|---|---|---|
| Read | Tells memory to send data to the data bus | CPU → Memory |
| Write | Tells memory to accept data from the data bus | CPU → Memory |
| Clock | Synchronises all operations to the system clock | CPU → All |
| Interrupt | A device requests CPU attention | I/O → CPU |
| Bus Request | A device requests control of the bus | I/O → CPU |
| Bus Grant | CPU grants bus control to a device | CPU → I/O |
| Reset | Resets the CPU to initial state | External → CPU |
How They Work Together
✓ Example: CPU Reads Data from Memory Address 1024
Step 1: CPU places address 1024 on the ADDRESS BUS
→ The address bus carries 1024 to memory
Step 2: CPU sends a READ signal on the CONTROL BUS
→ Memory knows it should send data, not receive it
Step 3: Memory finds the data at address 1024
Step 4: Memory places the data onto the DATA BUS
→ Data travels from memory back to CPU
Step 5: CPU receives the data from the data bus
→ Data is placed into the MDR register✓ Example: CPU Writes Data to Memory Address 2048
Step 1: CPU places address 2048 on the ADDRESS BUS
Step 2: CPU places the data value on the DATA BUS
Step 3: CPU sends a WRITE signal on the CONTROL BUS
→ Memory knows it should store the data
Step 4: Memory stores the data at address 2048Comparison Table
| Feature | Address Bus | Data Bus | Control Bus |
|---|---|---|---|
| Carries | Memory addresses | Data & instructions | Control signals |
| Direction | Unidirectional (CPU→) | Bidirectional (CPU↔) | Bidirectional |
| Width affects | Max addressable memory | Transfer speed | N/A (individual lines) |
| Example signals | 0x0400 (address 1024) | 01101010 (data byte) | READ, WRITE, CLOCK |
Pitfalls & Common Errors
Saying the Address Bus Is Bidirectional
The address bus is unidirectional — only the CPU sends addresses. Memory never sends addresses back to the CPU.
Confusing Address Bus Width with Data Bus Width
Address bus width determines how many memory locations can be accessed. Data bus width determines how much data is transferred per cycle. They are different values.
Forgetting the Control Bus
Students often describe only address and data buses. Without the control bus, memory wouldn't know if it should read or write. Always include all three buses.
Pro-Tips for Exams
Answering Bus Questions
- Always describe all three buses even if the question seems to focus on one
- State: what the bus carries, its direction, and give an example of its use
- For "explain how data is transferred" questions — walk through a READ or WRITE scenario step-by-step
- Remember: Address bus width → addressable memory; Data bus width → transfer speed
Graded Tasks
Name the three components of the system bus. State what each carries and its direction.
Explain why the address bus is unidirectional while the data bus is bidirectional.
Calculate the maximum addressable memory for a system with a 24-bit address bus, assuming each address stores 1 byte.
Describe step-by-step how the CPU reads the value at memory address 512 using all three buses.
A 32-bit computer is upgraded to a 64-bit data bus but keeps its 32-bit address bus. Explain what improvements the user would notice and what limitation would remain.