Fetch-Decode-Execute Cycle
The Fetch-Decode-Execute (FDE) cycle is the fundamental process by which a CPU executes instructions. Every program you run — from opening a browser to calculating 2 + 3 — follows this cycle billions of times per second. Understanding the FDE cycle means understanding how a computer actually works at its core.
Learning Objectives
- 12.3.2.5 Explain three operations in a fetch-execute cycle (fetch / decode / execute)
Video Explanation
Watch a visual walkthrough of this topic
Conceptual Anchor
The Chef's Recipe Analogy
Imagine a chef preparing a multi-step recipe. FETCH = the chef reads the next line of the recipe. DECODE = the chef understands what the instruction means ("dice the onions" → need a knife, cutting board, onions). EXECUTE = the chef performs the action (actually dices the onions). Then the cycle repeats for the next instruction. A CPU does exactly this — billions of times per second.
Key CPU Registers
Before understanding the FDE cycle, you need to know the registers involved. Registers are tiny, ultra-fast storage locations inside the CPU.
| Register | Full Name | Purpose |
|---|---|---|
| PC | Program Counter | Holds the address of the next instruction to be fetched |
| MAR | Memory Address Register | Holds the address of the memory location being read/written |
| MDR | Memory Data Register | Holds the data read from or to be written to memory |
| CIR | Current Instruction Register | Holds the instruction currently being decoded/executed |
| ACC | Accumulator | Holds the result of arithmetic/logic operations |
MDR vs MBR
Some textbooks use MBR (Memory Buffer Register) instead of MDR. They mean the same thing — a temporary holding area for data being transferred between CPU and memory.
The Three Stages
1 FETCH
The CPU retrieves the next instruction from main memory (RAM).
Step 1: The address in the PC is copied to the MAR
PC → MAR
Step 2: The instruction at that memory address is fetched
via the address bus and loaded into the MDR
Memory[MAR] → MDR
Step 3: The instruction in MDR is copied to the CIR
MDR → CIR
Step 4: The PC is incremented by 1 (to point to next instruction)
PC ← PC + 12 DECODE
The Control Unit (CU) interprets the instruction in the CIR. It splits the instruction into:
Instruction format: [OPCODE] [OPERAND]
OPCODE = the operation to perform (e.g., LOAD, ADD, STORE, JUMP)
OPERAND = the data or memory address to use
Example: ADD 105
OPCODE = ADD (perform addition)
OPERAND = 105 (use data at memory address 105)The CU determines what signals to send, which components are needed (ALU, memory, I/O), and prepares them.
3 EXECUTE
The CPU carries out the instruction. The action depends on the type of instruction:
| Instruction Type | What Happens | Example |
|---|---|---|
| Data transfer | Data moves between registers/memory | LOAD R1, 100 → load value from address 100 into R1 |
| Arithmetic | ALU performs calculation, result in ACC | ADD R1, R2 → ACC = R1 + R2 |
| Logic | ALU performs comparison or logical op | CMP R1, R2 → compare R1 and R2 |
| Branch / Jump | PC is changed to a different address | JMP 200 → PC = 200 (skip to address 200) |
| I/O | Data transferred to/from I/O device | OUT R1 → send R1 value to output device |
Worked Example — Trace Through
Let's trace the execution of a simple program that loads two numbers, adds them, and stores the result.
Program in Memory
| Address | Instruction | Meaning |
|---|---|---|
| 100 | LDA 200 | Load value at address 200 into ACC |
| 101 | ADD 201 | Add value at address 201 to ACC |
| 102 | STO 202 | Store ACC value in address 202 |
| … | … | … |
| 200 | 15 | Data: 15 |
| 201 | 27 | Data: 27 |
| 202 | 0 | Data: (empty, will hold result) |
Cycle 1: LDA 200
| Stage | Action | Register Values |
|---|---|---|
| FETCH | PC(100)→MAR; Memory[100]→MDR; MDR→CIR; PC←101 | PC=101, MAR=100, MDR="LDA 200", CIR="LDA 200" |
| DECODE | CU splits: OPCODE=LDA, OPERAND=200 | — |
| EXECUTE | MAR←200; Memory[200]→MDR; MDR→ACC | ACC = 15 |
Cycle 2: ADD 201
| Stage | Action | Register Values |
|---|---|---|
| FETCH | PC(101)→MAR; Memory[101]→MDR; MDR→CIR; PC←102 | PC=102, CIR="ADD 201" |
| DECODE | CU splits: OPCODE=ADD, OPERAND=201 | — |
| EXECUTE | MAR←201; Memory[201]→MDR; ACC←ACC+MDR | ACC = 15 + 27 = 42 |
Cycle 3: STO 202
| Stage | Action | Register Values |
|---|---|---|
| FETCH | PC(102)→MAR; Memory[102]→MDR; MDR→CIR; PC←103 | PC=103, CIR="STO 202" |
| DECODE | CU splits: OPCODE=STO, OPERAND=202 | — |
| EXECUTE | MAR←202; MDR←ACC; MDR→Memory[202] | Memory[202] = 42 |
Pitfalls & Common Errors
Forgetting PC Increments During Fetch
The PC increments by 1 during every fetch stage (not after execute). This is crucial — examiners check for this step explicitly.
Confusing MDR and MAR
MAR holds addresses (where to look). MDR holds data (what was found there). Think: MAR = postcode, MDR = the letter inside the mailbox.
Skipping the CIR
Students often go straight from MDR to execution. The instruction must be copied from MDR → CIR first. The CIR holds the instruction while the MDR is freed for the execute stage.
Pro-Tips for Exams
Writing FDE Cycle Answers
- Always describe all 4 fetch sub-steps: PC→MAR, Memory→MDR, MDR→CIR, PC+1
- For decode: mention the Control Unit splitting instruction into opcode + operand
- For execute: describe the specific action (depends on instruction type)
- Use register names (PC, MAR, MDR, CIR, ACC) — this is what earns marks
- If asked "what role does the [register] play?" — explain using the FDE context
Graded Tasks
Name the 5 key registers in the FDE cycle and state the purpose of each.
Explain why the instruction is moved from MDR to CIR before execution begins.
Trace through the FDE cycle for the instruction "SUB 305" if the PC is currently 104 and the ACC contains 50. Address 305 contains the value 12. Show all register changes.
Explain what would happen if the PC did not increment during the fetch stage. How would this affect program execution?
Write a simple 5-instruction assembly program and trace through all 5 FDE cycles, showing the values of PC, MAR, MDR, CIR, and ACC after each stage.