Unit 11.1A · Term 1

Von Neumann Architecture

Nearly every modern computer follows the Von Neumann architecture, designed in 1945. It describes how a CPU fetches instructions from memory, processes them, and interacts with input/output devices.

Learning Objectives

  • 11.3.2.1 Describe the interaction of CPU with peripheral devices

Lesson Presentation

11.1A-von-neumann.pdf · Slides for classroom use

Conceptual Anchor

The Kitchen Analogy

A CPU is like a chef. The recipe (program) is in a cupboard (memory). The chef fetches one instruction, reads (decodes) it, and executes it. Ingredients come from input (delivery), finished dishes go to output (serving window).

Rules & Theory

Architecture Diagram

┌───────────────────────────┐ │ CPU │ │ ┌─────┐ ┌─────────┐ │ │ │ CU │ │ ALU │ │ │ └──┬───┘ └────┬────┘ │ │ │ Registers │ │ │ │ ACC,PC,MAR │ │ │ │ MDR, CIR │ │ └─────┼─────────────┼────────┘ │ SYSTEM BUS │ ══════╪═════════════╪════════ ┌─────┴─────────────┴──────┐ │ MAIN MEMORY │ │ (Instructions + Data) │ └──────────────────────────┘ / \ ┌──────────┐ ┌──────────┐ │ INPUT │ │ OUTPUT │ │ keyboard │ │ monitor │ │ mouse │ │ printer │ └──────────┘ └──────────┘

Key Principles

Principle Description
Stored Program Instructions and data stored in the same memory
Sequential Execution Instructions fetched and executed one at a time
Single Memory One memory for data + instructions (unlike Harvard)
Binary All data represented in binary

CPU Components

Component Full Name Purpose
CU Control Unit Directs operations, sends control signals, manages FDE cycle
ALU Arithmetic Logic Unit Performs calculations and logic (AND, OR, NOT)
ACC Accumulator Stores the result of ALU operations
PC Program Counter Holds address of the NEXT instruction
MAR Memory Address Register Holds address being accessed in memory
MDR Memory Data Register Holds data being transferred to/from memory
CIR Current Instruction Register Holds instruction being decoded/executed

Fetch-Decode-Execute (FDE) Cycle

FETCH: 1. PC contains address of next instruction 2. PC copied to MAR 3. CU sends READ signal via control bus 4. Instruction copied into MDR 5. MDR copied into CIR 6. PC incremented (PC = PC + 1) DECODE: 7. CU decodes instruction in CIR 8. CU determines what operation is needed EXECUTE: 9. CU sends signals to appropriate component 10. ALU performs calculation (if needed) 11. Result stored in ACC or memory → Cycle repeats

CPU ↔ Peripheral Interaction

Peripheral Type Direction How CPU Interacts
Input (keyboard) Peripheral → CPU Sends interrupt; CPU reads data via I/O bus
Output (monitor) CPU → Peripheral CPU sends data + control signals
Storage (SSD) Both CPU reads/writes via controller

Von Neumann Bottleneck

Instructions and data share the same bus, so they can't be fetched simultaneously. Solutions: cache memory, Harvard architecture (separate buses).

Common Pitfalls

PC = Personal Computer

Here PC = Program Counter — a register holding the address of the next instruction.

Tasks

Remember

Name the 3 stages of the FDE cycle.

Understand

Explain the role of MAR and MDR during a memory read.

Apply

Trace one FDE cycle for "ADD 5" at memory address 100.

Analyze

Explain the Von Neumann bottleneck and suggest two solutions.

Self-Check Quiz

Q1: What is the "stored program concept"?

Both instructions and data are stored in the same main memory.

Q2: What does the Program Counter do?

Holds the memory address of the next instruction to be fetched.

Q3: What is the difference between CU and ALU?

CU manages and coordinates all operations. ALU performs arithmetic and logic operations.